Controlling packaging encapsulant leakage

ABSTRACT

An integrated circuit package may be formed in part with an encapsulated region. Outflow of the encapsulant across critical electrical elements can be prevented by providing a cavity which collects encapsulant outflow between the region of encapsulation and the region where the critical components are situated. In one embodiment of the present invention, a surface may include a first portion covered by solder resist, having an area populated by bond pads, and a second portion which is encapsulated. Encapsulant flow over the bond pads is prevented by forming an opening in the solder resist proximate to the second portion to collect the encapsulant before it reaches the bond pads.

BACKGROUND

[0001] This invention relates generally to packaging electroniccomponents and in particular embodiments to encapsulating laminatepackages.

[0002] Laminate packages may be made of alternating core material andconductive layers. The core acts as a stiffener and insulator while theconductive layers are etched to leave a trace for electrical purposes.The laminate structure may have a solder resist selectively screenprinted onto specific areas of the structure for solder protection.

[0003] A laminate package may be encapsulated by enclosing theunencapsulated package inside two halves of a mold. At the juncture ofthe two mold faces, encapsulants sometimes leak forming what is known asflash. The encapsulant leaking between the two mold halves may actuallycontaminate the electrical components that come in contact with theencapsulant. Generally when this happens, the devices are deemeddefective and the entire laminated package is discarded.

[0004] In some cases, the leakage of encapsulant material is a result ofthe bleeding out of the resin vehicle from the overall epoxy. See,Ireland, James E., “Epoxy Bleeding Out in Ceramic Chip Carriers,” ISHMJournal, Vol. 5, No. 1. Regardless of whether the contamination occursbecause of the bleed out of the resin vehicle from the overall adhesiveor from the leakage of the overall resin itself, the effects of suchleakage on electronic components may be catastrophic.

[0005] Thus, there is a need to prevent flash contamination of theelectrical components of electrical packages and particularly forpreventing such contamination in the course of encapsulating laminatepackages.

SUMMARY

[0006] In accordance with one aspect, a process for encapsulatingintegrated circuits includes defining an encapsulation cavity about anintegrated circuit die. The cavity is filled with an encapsulant. Theoutflow of encapsulant is controlled by providing a collection reservoirproximate to the cavity.

[0007] Other aspects are set forth in the accompanying specification andclaims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1 is a greatly enlarged top plan view of one embodiment ofthe present invention;

[0009]FIG. 2 is an enlarged cross-sectional view taken generally alongthe line 2-2 in FIG. 1 when the device shown in FIG. 1 is in positionwithin an encapsulation mold;

[0010]FIG. 3 is a greatly enlarged cross-sectional view of a portion ofthe device shown in FIG. 2 in the process of being molded; and

[0011]FIG. 4 is an enlarged cross-sectional view taken generally alongthe line 2-2 in the embodiment shown in FIG. 1 after the device has beencompleted by attaching solder balls.

DETAILED DESCRIPTION

[0012] Referring to FIG. 1, a laminate package 10 may include anI-shaped core 11 punctuated by alignment openings 12. A centralencapsulated region 14 is bounded on either side by a flash cavity 16and a plurality of ball pads 20. Each ball pad is situated inside theopening left in a solder resist coating whose extent is defined by theedges 18. Each of the cavities 16 basically provides an effectivebarrier to encapsulant intended to form the region 14. However, withoutthe interposition of the cavities 16, encapsulant could extend outwardlyfrom the region 14 and overflow onto the pads 20. This could result incontamination and possible destruction of the core 11.

[0013] Referring to FIG. 2, the core 11 may be affixed to an integratedcircuit chip or die 30. Any conventional die affixation technique may beutilized. For example, the die 30 may be secured to the core 11 usingadhesive, such as epoxy, adhesive tape such as lead-on-chip (LOC) tapeor any other available technique. Wire bond wires 26 may make contactwith contacts on the die 30 and extend upwardly to make electricalcontact to corresponding contacts on the upper surface of the core 11.The bond wires 26 extend through the passage 25 which is filled withencapsulant 14.

[0014] The laminate package 10 may be encapsulated between two moldhalves 32 a and 32 b. The mold halves define a parting line 34. Theupper mold half 32 a includes an elliptical chamber 35 which defines theencapsulated region 14.

[0015] While in the mold, the encapsulated region 14 is filled with anencapsulant. The encapsulant pots the bond wires 26 that are bonded onone end to the die 30 and extend upwardly to contact the upper surfaceof the core 11. The wires 26 make contact with contacts 24 (shown inFIG. 4) situated between a cavity 16 and the region 14.

[0016] Referring to FIG. 3, encapsulant “A” from the region 14 may tendto extend outwardly along the parting line 34. In such case, it flowsover the solder resist 18 and into the cavity 16 defined in the solderresist 18. Thus, the cavity 16 provides a reservoir to collect theencapsulant overflow. The encapsulant readily fills the reservoir 16because of its greater open area which provides pressure relief to theencapsulant which squeezes out between any slight gaps between the moldhalves 32 a and 32 b. Thus, the encapsulant flows along the parting line34 when the two mold halves 32 a and 32 b are not perfectly pressedtogether. The overflowing encapsulant then flows into the cavity 16where it may be retained until it solidifies. In this way, the flow inthe direction of the arrows A is blocked from extending to the pads 20to the left in FIG. 3.

[0017] Because the cavity 16 may be simply formed by appropriatepatterning of the solder resist 18, the provision of the cavities isrelatively inexpensive if not cost free. Since apertures must be definedin the solder resist to form the edges 18 surrounding the bond pads 20,the pattern for the cavities 16 may be included at the same time. Thatis, the cavity 16 on either side of the encapsulated region 14 may bedefined during the process of patterning the solder resist to form theopenings that define the edges 18 around pads 20.

[0018] Referring now to FIG. 4, which shows the device of FIG. 1 incross-section after solder balls 28 have been positioned, the die 30 isoverlaid by the laminate package 10 which has the central opening 25which is filled with encapsulant. The upper surface of the encapsulatedregion 14 may have an elliptical configuration, in one example, becauseof the shape of the upper mold half 32 a (FIG. 2). As a result, the bondwires 26, which extend from the die 30 up to the contacts 24 on theupper surface of the laminate package 10, are completely potted.

[0019] The mold half 32 b may define a cavity 50 for encapsulating thedie 30 as shown in FIG. 2. The encapsulation 52 then covers the die 30,as shown in FIG. 4.

[0020] The contacts 24 may electrically communicate, via traces 22 whichextend through the core 11, with various pads 20. The pads 20 may inturn electrically couple to solder balls 28 in a conventional flip-chipor ball grid array packaging embodiment. Thus, the solder balls 28 arecapable of communicating with the world outside of the package 10. Inthis way, the laminate package 10 provides a convenient interconnectionmedium for allowing the die 30 to communicate with external devices.

[0021] The solder resist includes the openings to define the edges 18 toallow for the imposition of the solder balls 28 as well as the openingswhich define the cavities 16 to receive any overflow of the encapsulantmaterial. By positioning a cavity 16 between the encapsulated region 14and the bond pads 20 for the solder balls 28, the critical electricalcontact areas can be protected from contamination by encapsulant flash.

[0022] While non-solder mask defined pads (NSDP) are illustrated, soldermask defined pads (SDP) may be used as well. Although a laminate packageis illustrated, other packaging configurations may be used as wellincluding those using an interposer.

[0023] While the present invention has been described with respect to alimited number of embodiments, those skilled in the art will appreciatenumerous modifications and variations therefrom. It is intended that theappended claims cover all such modifications and variations as fallwithin the true spirit and scope of this present invention.

What is claimed is:
 1. A process for encapsulating integrated circuitscomprising: defining an encapsulation chamber about an integratedcircuit die; filling said chamber with an encapsulant; and controllingoutflow of encapsulant from said chamber by providing a collectioncavity proximate to said chamber.
 2. The method of claim 1 furtherincluding connecting a die to a first side of a support structure andmaking electrical connections from said die through an opening in saidstructure to a second side of said structure.
 3. The method of claim 2including covering the second side of said structure with a solderresist and leaving bond pad openings in said solder resist.
 4. Themethod of claim 3 further including defining a solder resist free regionto define said collection cavity proximate to said chamber.
 5. Themethod of claim 4 including defining a plurality of ball pads on saidstructure adjacent said opening and positioning said cavity between saidopening and said ball pads.
 6. The method of claim 5 further includingsecuring a plurality of solder balls to said ball pads.
 7. The method ofclaim 1 wherein said cavity is formed in packaging associated with saiddie.
 8. The method of claim 1 including physically coupling said die toa structure, electrically coupling said die to said structure, providingbond pads on said structure, and positioning said cavity on saidstructure.
 9. The method of claim 8 including providing a passagethrough said structure for wires to couple said die to said structure,filling said passage with encapsulant, and positioning said cavitybetween said bond pads and said passage.
 10. A support structure for anintegrated circuit die comprising: a first surface including a bond pad;a first region defined in said first surface to receive encapsulant; anda cavity defined in said first surface between a bond pad and saidregion, said cavity adapted to collect encapsulant overflow from saidopening.
 11. The structure of claim 10 including a laminate body, saidfirst surface defined on said laminate body.
 12. The structure of claim10 including a body, said body covered by a solder resist layer, saidsolder resist layer defining said first surface.
 13. The structure ofclaim 12 including an opening in said solder resist layer for said bondpad.
 14. The structure of claim 13 wherein said cavity is defined by anopening in said solder resist layer.
 15. The structure of claim 14wherein said cavity is defined by an area where no solder resist existsover said body.
 16. The structure of claim 11 wherein said region isdefined by an opening extending through said laminate body.
 17. A methodfor encapsulating an electronic device comprising: encapsulating atleast a portion of said electronic device; and preventing outflow ofencapsulation material from said encapsulated portion to anon-encapsulated portion by providing an encapsulation receiving cavitybetween said encapsulated portion and said non-encapsulated portion. 18.The method of claim 17 including covering said non-encapsulated portionwith a solder resist material, forming at least one opening in saidsolder resist material for a bond pad, and forming said cavity byforming a second opening in said solder resist material.
 19. The methodof claim 18 including defining said cavity between a bond pad and saidencapsulated region.
 20. The method of claim 19 including patterningsaid solder mask material to form an opening for said bond pad and toform an opening to create said cavity.
 21. A laminate packagecomprising: a laminate core having an opening through said core from afirst side of said core to a second side of said core; a die coupled tosaid core on said first side of said core; a bond pad defined on saidsecond side of said core; and an encapsulation flash receiving cavitybetween said bond pads and said opening.
 22. The package of claim 21including a solder resist material on said second side, said solderresist material having an opening for said bond pad.
 23. The package ofclaim 22 including an opening in said solder resist to define saidcavity.
 24. The package of claim 23 including wire bond wires extendingfrom said die to said second side of said core.
 25. The package of claim24 including a bond pad on either side of said opening, and a cavitypositioned on each side of said opening between said opening and a bondpad.
 26. A method for packaging integrated circuit devices comprising:defining an encapsulated region on a support structure; defining bondpads on an unencapsulated region of said support structure; depositing asolder resist material on said unencapsulated portion of said supportstructure; and defining openings in said solder resist material for saidbond pads and defining an additional opening between said bond pads andsaid encapsulated region to collect encapsulation overflow from saidencapsulated region.
 27. The method of claim 26 including attaching adie to said support structure.
 28. The method of claim 27 includingforming an opening through said support structure and wire bonding a dieattached to one side of said support structure to contacts on saidsecond side of said support structure.
 29. The method of claim 28including encapsulating said opening to form said encapsulated region.30. The method of claim 26 including defining the openings for said bondpads and for said cavity by patterning said solder resist layer.